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 HD74AC107/HD74ACT107
Dual JK Flip-Flop (with Separate Clear and Clock)
REJ03D0243-0200Z (Previous ADE-205-363 (Z)) Rev.2.00 Jul.16.2004
Description
The HD74AC107/HD74ACT107 dual JK master/slave flip-flops have a separate clock for each flip-flop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the state of the coupling transistors which connect the master and slave sections. The sequence of operation is as follows: 1) isolate slave from master; 2) enter information from J and K inputs to master; 3) disable J and K inputs; 4) transfer information from master to slave.
Features
* Outputs Source/Sink 24 mA * HD74ACT107 has TTL-Compatible Inputs * Ordering Information: Ex. HD74AC107
Part Name HD74AC107FPEL HD74AC107RPEL Package Type SOP-14 pin (JEITA) Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-14DAV FP RP EL (2,000 pcs/reel) EL (2,500 pcs/reel)
SOP-14 pin (JEDEC) FP-14DNV
Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code.
Pin Arrangement
J1 1 Q1 2 Q1 3 K1 4 Q2 5 Q2 6 GND 7 (Top view) 14 VCC 13 CD1 12 CP1 11 K2 10 CD2 9 CP2 8 J2
Rev.2.00, Jul.16.2004, page 1 of 6
HD74AC107/HD74ACT107
Logic Symbol
1 12 4 J1 CP1 K1 Q1 2 Q1 3 8 9 11 J2 CP2 K2 Q2 5 Q2 6
CD1 13
CD2 10
VCC = Pin14 GND = Pin7
Pin Names
J1, J2, K1, K2 CP1, CP2 CD1, CD2 Q1, Q2, Q1, Q 2 Data Inputs Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active Low) Outputs
Truth Table
Inputs @ tn J L L H H H L tn tn + 1 L H L H : : : : High Voltage Level Low Voltage Level Bit time before clock pulse. Bit time after clock pulse. K Qn L H Qn Outputs @ tn + 1 Q
Logic Diagram
CD J K CP #CP #CP #CP Q Q CP #CP
CP CP CP CP
CP
Rev.2.00, Jul.16.2004, page 2 of 6
HD74AC107/HD74ACT107
Absolute Maximum Ratings
Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C Condition VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V
Recommended Operating Conditions: HD74AC107
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition
DC Characteristics: HD74AC107
Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* IIN IOLD IOHD 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- Ta = -40 to +85C min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 40 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition
Input Voltage
V
VOUT = 0.1 V or VCC -0.1 V
Output voltage
VOH
VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground
Quiescent supply 5.5 -- -- 4.0 ICC current *Maximum test duration 2.0 ms, one output loaded at a time.
Rev.2.00, Jul.16.2004, page 3 of 6
HD74AC107/HD74ACT107
Recommended Operating Conditions: HD74ACT107
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 0.8 to 2.0 V Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 4.5V VCC = 5.5V Unit Condition
DC Characteristics: HD74ACT107
Item Symbol VIH VIL Output voltage VOH VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 VOL 5.5 4.5 5.5 4.5 Input current ICC/input current Dynamic output current* Quiescent supply current IIN ICCT IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 5.5 min. 2.0 2.0 -- -- 4.4 5.4 3.94 4.94 -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 1.5 1.5 1.5 4.49 5.49 -- -- 0.001 0.001 -- -- -- 0.6 -- -- -- max. -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.32 0.32 0.1 -- -- -- 4.0 Ta = -40 to +85C min. 2.0 2.0 -- -- 4.4 5.4 3.80 4.80 -- -- -- -- -- -- 86 -75 -- max. -- -- 0.8 0.8 -- -- -- -- 0.1 0.1 0.37 0.37 1.0 1.5 -- -- 40 A mA mA mA A V Unit Condition
Input voltage
V
VOUT = 0.1 V or Vcc-0.1 V VOUT = 0.1 V or Vcc-0.1 V VIN = VIL or VIH IOUT = -50 A VIN = VIL VIN = VIL or VIH IOUT = 50 A VIN = VIL VIN = VCC or GND VIN = VCC-2.1 V VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground IOL = 24 mA IOL = 24 mA IOH = -24 mA IOH = -24 mA
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics: HD74AC107
Ta = +25C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD to Q Propagation delay Symbol fmax tPLH tPHL tPLH tPHL VCC (V)*1 Min 3.3 125 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 150 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Typ -- -- 9.5 7.5 10.0 8.0 9.5 7.5 9.5 7.5 Max -- -- 13.0 10.0 13.5 10.5 13.0 10.0 13.0 10.0 Ta = -40C to +85C CL = 50 pF Min 100 125 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Max -- -- 14.0 11.0 14.5 11.5 14.0 11.0 14.0 11.0 MHz ns ns ns ns Unit
5.0 CD to Q Note: 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 6
HD74AC107/HD74ACT107
Operating Requirements: HD74AC107
Ta = +25C CL = 50 pF Item Setup time J or k to CP Hold time CP to J or k Pulse width CP or CD Recovery time CD to CP Note: Symbol VCC (V)*1 Typ tsu 3.3 3.0 th tw trec 5.0 3.3 5.0 3.3 5.0 3.3 5.0 2.0 -1.5 -0.5 2.0 2.0 1.5 1.0 Ta = -40C to +85C CL = 50 pF Unit ns
Guaranteed Minimum 5.5 6.0 4.0 0.0 0.0 5.5 4.5 3.0 3.0 4.5 0.0 0.0 7.0 5.0 3.0 3.0
1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
AC Characteristics: HD74ACT107
Ta = +25C CL = 50 pF Item Maximum clock frequency Propagation delay CP to Q or Q Propagation delay CP to Q or Q Propagation delay CD to Q Propagation delay CD to Q Note: Symbol fmax tPLH tPHL tPLH tPHL VCC (V)*1 Min 5.0 100 5.0 5.0 5.0 5.0 1.0 1.0 1.0 1.0 Typ -- 9.5 10.5 8.5 8.5 Max -- 12.5 13.0 11.0 11.0 Ta = -40C to +85C CL = 50 pF Min 80 1.0 1.0 1.0 1.0 -- 13.5 14.0 12.0 12.0 Max MHz ns Unit
1. Voltage Range 5.0 is 5.0 V 0.5 V
Operating Requirements: HD74ACT107
Ta = +25C CL = 50 pF Item Setup time J or k to CP Hold time 5.0 th CP to J or k Pulse width tw 5.0 CP or CD Recovery time trec 5.0 CD to CP Note: 1. Voltage Range 5.0 is 5.0 V 0.5 V Symbol VCC (V)*1 Typ tsu 5.0 2.5 0.0 4.5 -- Ta = -40C to +85C CL = 50 pF Unit ns
Guaranteed Minimum 7.0 8.0 1.5 7.0 3.0 1.5 8.0 3.0
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 35.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
Rev.2.00, Jul.16.2004, page 5 of 6
HD74AC107/HD74ACT107
Package Dimensions
As of January, 2003
Unit: mm
10.06 10.5 Max 14 8
5.5
1
7
*0.20 0.05 2.20 Max
0.20 7.80 + 0.30 -
1.42 Max
1.15 0 - 8 0.70 0.20
1.27 *0.40 0.06
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-14DAV -- Conforms 0.23 g
*Ni/Pd/Au plating
0.10 0.10
0.15
As of January, 2003
Unit: mm
8.65 9.05 Max 14 8
3.95
1
1.75 Max
*0.20 0.05
7
6.10 - 0.30 1.08
+ 0.10
0.635 Max
0 - 8
+ 0.11
1.27 *0.40 0.06
0.14 - 0.04
0.67 0.60 + 0.20 -
0.15 0.25 M
Package Code JEDEC JEITA Mass (reference value) FP-14DNV Conforms Conforms 0.13 g
*Ni/Pd/Au plating
Rev.2.00, Jul.16.2004, page 6 of 6
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
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